Discontinued (8/99 - last order; 12/99 - last ship)
IBM0364804 IBM0364164
IBM0364404 IBM03644B4
64Mb Synchronous DRAM - Die Revision B
Read and Write Access Modes
After a bank has been activated, a read or write cycle can be executed. This is accomplished by setting RAS
high and CAS low at the clock’s rising edge after the necessary RAS to CAS delay (tRCD). WE must also be
defined at this time to determine whether the access cycle is a read operation (WE high), or a write operation
(WE low). The address inputs determine the starting column address.
The SDRAM provides a wide variety of fast access modes. A single Read or Write Command will initiate a
serial read or write operation on successive clock cycles at data rates of up to 147 MHz. The number of serial
data bits for each access is equal to the burst length, which is programmed into the Mode Register. If the
burst length is full page, data is repeatedly read out or written until a Burst Stop or Precharge Command is
issued.
Similar to Page Mode of conventional DRAMs, a read or write cycle can not begin until the sense amplifiers
latch the selected row address information. The refresh period (tREF) is what limits the number of random col-
umn accesses to an activated bank. A new burst access can be done even before the previous burst ends.
The ability to interrupt a burst operation at every clock cycle is supported; this is referred to as the 1-N rule.
When the previous burst is interrupted by another Read or Write Command, the remaining addresses are
overridden by the new address.
Precharging an active bank after each read or write operation is not necessary, providing the same row is to
be accessed again. To perform a read or write cycle to a different row within an activated bank, the bank must
be precharged and a new Bank Activate command must be issued. When more than one bank is activated,
interleaved (ping pong) bank Read or Write operations are possible. By using the programmed burst length
and alternating the access and precharge operations between multiple banks, fast and seamless data access
operation among many different pages can be realized. When multiple banks are activated, column to column
interleave operation can be done between different pages. Finally, Read or Write Commands can be issued
to the same bank or between active banks on every clock cycle.
Burst Read Command
The Burst Read command is initiated by having CS and CAS low while holding RAS and WE high at the rising
edge of the clock. The address inputs determine the starting column address for the burst. The Mode Regis-
ter sets the type of burst (sequential or interleave) and the burst length (1, 2, 4, 8, full page). The delay from
the start of the command to when the data from the first cell appears on the outputs is equal to the value of
the CAS latency that is set in the Mode Register.
Burst Read Operation
(Burst Length = 4, CAS Latency = 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 2
DOUT A0
DOUT A1
DOUT A0
DOUT A2
DOUT A1
DOUT A3
DOUT A2
tCK2, DQs
CAS latency = 3
DOUT A3
tCK3, DQs
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
19L3264.E35855A
1/28/99
Page 12 of 72
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