IBM0316409C IBM0316809C
IBM0316169C
16Mbit Synchronous DRAM
Read Interrupted by a Read
A Burst Read may be interrupted before completion of the burst by another Read Command, with the only
restriction being that the interval that separates the commands must be at least one clock cycle. When the
previous burst is interrupted, the remaining addresses are overridden by the new address with the full burst
length. The data from the first Read Command continues to appear on the outputs until the CAS latency from
the interrupting Read Command is satisfied, at this point the data from the interrupting Read Command
appears.
(Burst Length = 4, CAS latency = 1, 2, 3)
T0
T1
T2
T3
T4
T5
T6
T7
T8
CLK
READ A
READ B
DOUT A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
COMMAND
CAS latency = 1
DOUT B
DOUT B
DOUT B
DOUT B
3
0
0
0
1
2
t
CK1, DQ’s
CAS latency = 2
DOUT A
DOUT B
DOUT B
DOUT B
DOUT B
DOUT B
0
1
2
3
t
CK2, DQ’s
CAS latency = 3
DOUT A
DOUT B
DOUT B
DOUT B
3
0
0
1
2
t
CK3, DQ’s
Read Interrupted by a Write
Dependent upon CAS Latency and burst length, there exist two methods in which a burst read operation can
be interrupted by a Write Command and one situation in which a burst read operation can not be interrupted
by a Write Command. To interrupt a burst read with a Write Command, DQM must be used to avoid data con-
tention on the I/O bus by placing the DQ’s (output drivers) in a high impedance state at least one clock cycle
before the Write Command is initiated. To insure the DQ’s are tri-stated one cycle before the write operation
begins, DQM must be activated at least 3 clock cycles before the Write Command and be deactivated in the
same clock cycle as the Write Command.
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
07H3997
SA14-4711-02
Revised 05/96
Page 13 of 100
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