Burst Length = Full Page, CAS Latency = 1
Full Page Write Cycle (1 of 3)
T0
T7
T1
T2
T3
T4
T5
T6
T8
T9
T10
T12
T17
T21
T11
T13
T14
T15
T16
T18
T19
T20
T22
CLK
tCK1
High
CKE
CS
RAS
CAS
WE
A11(BS)
RAx
RBx
RBy
RBy
A10
RAx
CAx
RBx
CBx
A0 - A9
DQM
DQ
Hi-Z
DAx DAx+1 DAx+2 DAx+2 DAx-1 DAx DAx+1 DBx DBx+1 DBx+2 DBx+3 DBx+4 DBx+5 DBx+6 DBx+7
Page Length:
Activate
Command
Bank B
Write
Command
Bank B
Precharge
Command
Bank B
2Mb x 4I/O x 2 Banks = 1024
1Mb x 8I/O x 2 Banks = 512
512kb x 16I/O x 2 Banks = 256
Data is ignored.
Activate
Command
Bank A
The burst counter wraps
from the highest order
page address back to zero
during this time interval.
Full Page burst operation does not
terminate when the burst length is satisfied;
the burst counter increments and continues
bursting beginning with the starting address.
Activate
Command
Bank B
Write
Command
Bank A
Burst Stop
Command
IBM [ IBM ]
