.
Advance 0.1
Features
• High Performance:
IBM0312164 IBM0312804
IBM0312404 IBM03124B4
128Mb Synchronous DRAM - Die Revision B
-75H
-75D
-75A, -260, -360, -10,
Units
CL=2 CL=3 CL=3 CL=2 CL=3 CL=3
Clock
f
CK
Frequency
t
CK
Clock Cycle
t
AC
Clock Access
Time
133
7.5
—
5.4
133
7.5
—
5.4
133
7.5
—
5.4
100
10
—
6
100
10
—
6
100
10
7
9
MHz
ns
ns
ns
• Programmable CAS Latency: 2, 3
• Programmable Burst Length: 1, 2, 4, 8
• Programmable Wrap: Sequential or Interleave
• Multiple Burst Read with Single Write Option
• Automatic and Controlled Precharge Command
• Data Mask for Read/Write control (x4, x8)
• Dual Data Mask for byte control (x16)
• Auto Refresh (CBR) and Self Refresh
• Suspend Mode and Power Down Mode
• Standard Power operation
• 4096 refresh cycles/64ms
• Random Column Address every CK (1-N Rule)
• Single 3.3V
±
0.3V Power Supply
• LVTTL compatible
• Package: 54-pin 400 mil TSOP-Type II
2 High Stack TSOJ
Clock Access
t
AC
Time
1.
2.
3.
Terminated load. See AC Characteristics on page 39.
Unterminated load. See AC Characteristics on page 39.
t
RP
= t
RCD
= 2 CKs
• Single Pulsed RAS Interface
• Fully Synchronous to Positive Clock Edge
• Four Banks controlled by BS0/BS1
(Bank Select)
Description
The IBM0312404, IBM0312804, and IBM0312164
are four-bank Synchronous DRAMs organized as
8Mbit x 4 I/O x 4 Bank, 4Mbit x 8 I/O x 4 Bank, and
2Mbit x 16 I/O x 4 Bank, respectively. IBM03124B4,
a stacked version of the x4 component, is also
offered. These synchronous devices achieve high-
speed data transfer rates of up to 133MHz by
employing a pipeline chip architecture that synchro-
nizes the output data to a system clock. The chip is
fabricated with IBM’s advanced 128Mbit single tran-
sistor CMOS DRAM process technology.
The device is designed to comply with all JEDEC
standards set for synchronous DRAM products,
both electrically and mechanically. All of the control,
address, and data input/output (I/O or DQ) circuits
are synchronized with the positive edge of an exter-
nally supplied clock.
RAS, CAS, WE, and CS are pulsed signals which
are examined at the positive edge of each externally
applied clock (CK). Internal chip operating modes
are defined by combinations of these signals and a
command decoder initiates the necessary timings
for each operation. A fourteen bit address bus
accepts address data in the conventional RAS/CAS
multiplexing style. Twelve row addresses (A0-A11)
06K7582.H03335
05/00
and two bank select addresses (BS0, BS1) are
strobed with RAS. Eleven column addresses (A0-
A9, A11) plus bank select addresses and A10 are
strobed with CAS. Column address A11 is dropped
on the x8 device, and column addresses A11 and
A9 are dropped on the x16 device. Access to the
lower or upper DRAM in a stacked device is con-
trolled by CS0 and CS1, respectively.
Prior to any access operation, the CAS latency,
burst length, and burst sequence must be pro-
grammed into the device by address inputs A0-A11,
BS0, BS1 during a mode register set cycle. In addi-
tion, it is possible to program a multiple burst
sequence with single write cycle for write through
cache operation.
Operating the four memory banks in an interleave
fashion allows random access operation to occur at
a higher rate than is possible with standard DRAMs.
A sequential and gapless data rate of up to 133MHz
is possible depending on burst length, CAS latency,
and speed grade of the device. Simultaneous opera-
tion of both decks of a stacked device is allowed,
depending on the operation being done. Auto
Refresh (CBR) and Self Refresh operation are sup-
ported.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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