IBM0165165B
IBM0165165P
ADVANCED
4M x 16 12/10 EDO DRAM
Self Refresh Cycle (Sleep Mode) - Low Power version only
tRASS
tRPS
VIH
RAS
VIL
tRPC
tCSR
tCRP
tCHS
tCP
VIH
VIL
UCAS
LCAS
tWRH
tWRP
VIH
VIL
WE
tOFF
VOH
VOL
DOUT
Hi-Z
: “H” or “L”
NOTE: Address and OE are “H” or “L”
Once tRASS (min) is provided and RAS remains low, the DRAM will be in Self Refresh,
commonly known as “Sleep Mode.”
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
27H6253
SA14-4239-02
10/96
Page 25 of 31