IBM014405M IBM014405
IBM014405P IBM014405B
1M x 4 10/10 EDO DRAM
Refresh Cycle
-60
-70
Symbol
Parameter
Units
Notes
Min.
5
Max.
—
Min.
5
Max.
—
CAS Setup Time
(CAS before RAS Refresh)
tCSR
tCHR
tWRP
ns
ns
ns
1
1
CAS Hold Time
(CAS before RAS Refresh)
10
10
10
—
—
—
10
10
10
—
—
—
WE Setup Time
(CAS before RAS Refresh)
WE Hold Time
(CAS before RAS Refresh)
tWRH
tRPC
ns
ns
RAS Precharge to CAS Hold Time
0
—
16
0
—
16
SP version
LP version
—
—
—
—
tREF
Refresh period
ms
2
128
128
1. Enables on-chip refresh and address counters.
2. 1024 cycles.
Self Refresh Cycle - Low Power version only
-60
-70
Symbol
Parameter
Units
Notes
Min.
100
110
10
Max.
—
Min.
Max.
µs
ns
ns
tRASS
tRPS
RAS Pulse Width (Self Refresh)
100
130
10
—
—
—
1,2
1
RAS Precharge Time During Self Refresh Cycle
CAS Hold Time During Self Refresh Cycle
—
tCHD
—
1
1. When using Self Refresh mode, the following refresh operations must be performed to ensure proper DRAM operation: If row
addresses are being refreshed in a EVENLY DISTRIBUTED manner over the refresh interval using CBR refresh cycles, then only
one CBR cycle must be performed immediately after exit from Self Refresh. If row addresses are being refreshed in a ROR man-
ner over the refresh interval, then a full burst of all row refreshes must be performed immediately before entry to and immediately
after exit from Self Refresh. If row addresses are being refreshed in a CBR-Burst manner over the refresh interval (i.e. burst of 8),
then upon exiting from Self Refresh the user must conform to whatever refresh (i.e. burst of 8) method that was being used prior to
entering Self Refresh.
2. I/O pins will go into high impedance after 100µs.
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
27H6242
SA14-4232-03
Revised 6/96
Page 10 of 29
IBM [ IBM ]
