IBM014405
IBM014405M
IBM014405B IBM014405P
1M x 4 10/10 EDO DRAM
Write Cycle (Delayed Write)
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tRSH
VIH
CAS
VIL
tCAS
tRAD
tASR
tASC
tRAH
tCAH
VIH
Address
Row
tWRP
Column
VIL
tWRH
tRCS
tCWL
VIH
VIL
tWP
NOTE 1
WE
OE
tRWL
VIH
VIL
tOEH
tDH
tOED
tDZO
tDS
tWRP
tDZC
VIH
VIL
DIN
Hi-Z
Valid Data In
tOEZ
tCLZ
tOEA
VOH
VOL
*
DOUT
Hi-Z
Hi-Z
*
tOEH greater than or equal to tCWL
: “H” or “L”
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
27H6242
SA14-4232-03
Revised 6/96
Page 13 of 29
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