IBM014405M IBM014405
IBM014405P IBM014405B
1M x 4 10/10 EDO DRAM
Self Refresh Cycle (Sleep Mode) - Low Power version only
tRASS
tRPS
VIH
RAS
VIL
tRPC
tCSR
tCRP
tCP
tCHD
VIH
VIL
CAS
WE
tWRH
tWRP
VIH
VIL
tOFF
VOH
VOL
DOUT
Hi-Z
: “H” or “L”
NOTE: Address and OE are “H” or “L”
Once RAS (min) is provided and RAS remains low, the DRAM will be in Self Refresh,
commonly known as “Sleep Mode.”
©IBM Corporation, 1996. All rights reserved.
Use is further subject to the provisions at the end of this document.
27H6242
SA14-4232-03
Revised 6/96
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