IBM0118165 IBM0118165M
IBM0118165B IBM0118165P
1M x 16 10/10 EDO DRAM
Read-Modify-Write Cycle
tRWC
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tRSH
VIH
tCAS
UCAS
LCAS
tRAD
VIL
tASR
tASC
tRAH
tCAH
VIH
Address
Row
Column
VIL
tCWD
tRWL
tCWL
tAWD
tWRH
tWRP
tRWD
tWP
VIH
VIL
NOTE 1
tAA
WE
OE
tRCS
tOEH
VIH
VIL
tOEA
tDZC
tDH
tDS
tDZO
VIH
VIL
DIN
Hi-Z
tCAC
DIN
tOED
tCLZ
tOEZ
VOH
VOL
*
Hi-Z
Hi-Z
DOUT
DOUT
*
tRAC
t
OEH greater than or equal to tCWL
NOTE 1: Implementing WE at RAS time During a Read or Write Cycle is optional.
: “H” or “L”
Doing so will facilitate compatibility with future EDO DRAMs.
©IBM Corporation, 1995. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4721
SA14-4223-01
Revised 12/95
Page 15 of 32
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