IBM0118160
IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
Write Cycle (Delayed Write)
tRC
tRAS
tRP
VIH
RAS
VIL
tCSH
tCRP
tRCD
tRSH
VIH
VIL
UCAS
LCAS
tCAS
tRAD
tASC
tASR
tRAH
tCAH
VIH
VIL
Address
Row
Column
tCWL
tRCS
VIH
VIL
tWP
WE
OE
tRWL
VIH
VIL
tOEH
tDH
tOED
tDZO
tDS
tDZC
VIH
VIL
Valid Data In
DIN
Hi-Z
tOEZ
tCLZ
tOEA
VOH
VOL
*
DOUT
Hi-Z
Hi-Z
*
tOEH greater than or equal to tCWL
: “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
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