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IBM0118160PT3-60 参数 Datasheet PDF下载

IBM0118160PT3-60图片预览
型号: IBM0118160PT3-60
PDF下载: 下载PDF文件 查看货源
内容描述: [Fast Page DRAM, 1MX16, 60ns, CMOS, PDSO44, 0.400 X 0.825 INCH, TSOP2-50/44]
分类和应用: 动态存储器光电二极管内存集成电路
文件页数/大小: 27 页 / 280 K
品牌: IBM [ IBM ]
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IBM0118160
IBM0118160M
IBM0118160B IBM0118160P
1M x 16 10/10 DRAM
Write Cycle
-50
Symbol
t
WCS
t
WCH
t
WP
t
RWL
t
CWL
t
DS
t
DH
Parameter
Min.
Write Command Set Up Time
Write Command Hold Time
Write Command Pulse Width
Write Command to RAS Lead Time
Write Command to CAS Lead Time
D
IN
Setup Time
D
IN
Hold Time
0
10
10
13
13
0
10
Max.
Min.
0
15
15
15
15
0
12
Max.
Min.
0
15
15
20
20
0
15
Max.
ns
ns
ns
ns
ns
ns
ns
2
2
1
-60
-70
Units
Notes
1. t
WCS
, t
RWD
, t
CWD
, t
AWD
and t
CPW
are not restrictive operating parameters. They are included in the data sheet as electrical charac-
teristics only. If t
WCS
t
WCS
(min), the cycle is an early write cycle and the data pin will remain open circuit (high impedance)
through the entire cycle. If t
RWD
t
RWD
(min), t
CWD
t
CWD
(min), t
AWD
t
AWD
(min), and t
CPW
t
CPW
(min)(Fast Page Mode), the
cycle is a Read-Modify-Write cycle and the data out will contain data read from the selected cell. If neither of the above sets of con-
ditions are satisfied, the condition of the data out (at access time) is indeterminate.
2. These parameters are referenced to LCAS or UCAS leading edge in early write cycles and to WE leading edge in Read-Modify-
Write cycles.
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
43G9388
SA14-4209-04
Revised 11/96
Page 8 of 26