Discontinued (9/98 - last order; 3/99 last ship)
IBM0117800 IBM0117800M
IBM0117800B IBM0117800P
2M x 8 11/10 DRAM
Block Diagram
I/O0
I/O7
Vss
Vcc
(5.0 Volt version)
(to OCDs)
8
8
Regulator
V
DD
(internal)
WE
Data In Buffer
Data Out Buffer
OE
&
8
8
CAS
CAS Clock
Generator
10
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
Column Address
Buffer (10)
Column Decoder and I/O Gate
10
Sense Amplifiers
8
Refresh
Controller
1024 x 8
Refresh Counter
(11)
Row Decoder
Memory Array
2048 x 1024 x 8
11
Row Address
Buffer (11)
11
11
2048
RAS
RAS Clock
Generator
43G9629
SA14-4205-07
Revised 4/97
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
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