IBM01164B0
IBM01164D0
4M x 4 Stacked DRAM
Hidden Refresh Cycle (Read)
tRC
tRC
tRP
tRP
tRAS
tRAS
VIH
RAS
VIL
tRCD
tRSH
tCRP
tCHR
VIH
VIL
CAS
tRAL
tWRH
tWRP
tRAD
tASC
tASR
tRAH
tCAH
VIH
VIL
Address
Row
Column
tRRH
tRCS
VIH
VIL
WE
OE
tAA
VIH
VIL
tOEA
tDZC
tCDD
tODD
tDZO
VIH
VIL
Hi-Z
DIN
tCAC
tCLZ
tOFF
tOEZ
VOH
VOL
DOUT
Valid Data Out
Hi-Z
Hi-Z
tRAC
tOH
tOHO
: “H” or “L”
©IBM Corporation. All rights reserved.
Use is further subject to the provisions at the end of this document.
28H4727
GA14-4248-01
Revised 11/96
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