IBM Microelectronics
ALDC1-5S
Data Compression
Product Part Number: IBM22-ALDC1005S
Document Number: DCALD5DSU-04
Figure 3-2. Status Register
Figure 3-3. EC Level Register
BIT
NAME/NOTES
BIT
NAME/NOTES
7
Busy
7:0
EC Level
This bit is set to one by
For ALDC1-5S, the value of these
ALDC1-5S when a data transfer
operation is initiated by micro-
processor and is reset to zero
when the transfer is completed
successfully, when an error
occurs, or when a reset occurs.
bits is B'11101100'.
3.1.3 Original Data Interface
Transfer Count (TCO)
UPADDR: X'2' and X'3'
Type: Read
6:4
3
Reserved
Expansion
The Original Data Interface Transfer Count
(TCO) register provides the number of bytes
transferred on the original data interface for a
current data transfer operation. TCO is a two
byte register with the most significant byte con-
tained in Original Data Interface Transfer Count
High (TCOH) and the least significant byte con-
tained in Original Data Interface Transfer Count
This bit is set to one when
ALDC1-5S detects that the Com-
pressed Data Interface Transfer
Count (TCC) register is larger
than the Original Data Interface
Transfer Count (TCO) register at
the end of a compression opera-
tion.
Low (TCOL). TCO is reset to X
hardware or software reset. Also, TCO is reset
to X 0000 when a data transfer operation is
initialized.
'0000' by a
See section 3.4 on page 3-6 for a
discussion of data expansion.
'
'
2
1
Reserved
Any Error
The Original Data Interface Transfer Count reg-
ister layout is given in Figure 3-4.
This bit is the logical OR of all
error bits in the Error Status
(ERRS) register.
During a compression operation, TCO is incre-
mented as each original data byte is received
by the original data interface. When TCO
equals XFR during compression, all bytes in the
compression operation have been received by
ALDC1-5S.
0
Done
This bit is set to one when
ALDC1-5S has completed a
current data transfer operation.
During a decompression operation, TCO is
incremented as each decompressed data byte
is sent by the original data interface.
3.1.2 EC Level (ECL)
UPADDR: X'1'
Type: Read
Figure 3-4 (Page 1 of 2). Original Data Inter-
face Transfer Count Register
The EC Level (ECL) register provides engi-
neering change information bits to the micro-
processor. ECL is never reset.
BIT
NAME/NOTES
15:8
Original Data Interface Transfer
Count (High)
The EC Level register layout is given in
Figure 3-3.
Accessed through address X
on the microprocessor interface.
'2'
(C) IBM CORP. 1993, 1994. ALL RIGHTS RESERVED. USE IS FURTHER SUBJECT TO THE PROVISIONS ON THE BACK OF THE TITLE PAGE.
3-2
IBM [ IBM ]
