Product Part Number: IBM22-ALDC1005S
Document Number: DCALD5DSU-04
ALDC1-5S
Data Compression
IBM Microelectronics
Chapter 3. Microprocessor Interface
3.1 Registers
ALDC1-5S has sixteen registers which are
addressed using a four bit address bus. Each
register is eight bits wide. ALDC1-5S expects a
single, encoded chip select which activates the
microprocessor interface and its registers.
Figure 3-1 shows the registers on ALDC1-5S.
Figure 3-1. ALDC1-5S Registers
UPADDR
MNEMONIC
STAT
REGISTER NAME
Status
REFERENCE
R/ W
R
X'0'
3.1.1
X'1'
ECL
EC Level
3.1.2 on
page 3-2
R
X'
X'
X'
X'
X'
2
'
TCOH
TCOL
TCCH
TCCL
ERRS
Original Data Interface Transfer
Count (High)
3.1.3 on
page 3-2
R
R
R
R
R
3'
Original Data Interface Transfer
Count (Low)
3.1.3 on
page 3-2
4'
Compressed Data Interface
Transfer Count (High)
3.1.4 on
page 3-3
5'
Compressed Data Interface
Transfer Count (Low)
3.1.4 on
page 3-3
6'
Error Status
3.1.5 on
page 3-3
X
'
7
'
Reserved
Command
X'
8
'
CMND
3.1.6 on
R/ W
page 3-4
X'9'
Reserved
X
'
A
'
XFRH
XFRL
Transfer Size (High)
3.1.7 on
page 3-4
R/ W
R/ W
X'
B
'
Transfer Size (Low)
3.1.7 on
page 3-4
X'
X'
X'
X'
C
'
'
Reserved
Reserved
Reserved
D
E'
F'
CCNF
Compressed Data Interface Con-
figuration
3.1.8 on
page 3-5
R/ W
The Status (STAT) register provides status bits
3.1.1 Status (STAT)
UPADDR: X'0'
Type: Read
to the microprocessor. STAT is reset to X
'00'
by a hardware or software reset.
The Status register layout is given in
Figure 3-2.
(C) IBM CORP. 1993, 1994. ALL RIGHTS RESERVED. USE IS FURTHER SUBJECT TO THE PROVISIONS ON THE BACK OF THE TITLE PAGE.
3-1
IBM [ IBM ]
