1HY5PS12421B(L)FP
1HY5PS12821B(L)FP
1HY5PS121621B(L)FP
1. Description
1.1 Device Features & Ordering Information
1.1.1 Key Features
• VDD ,VDDQ =1.8 +/- 0.1V
• All inputs and outputs are compatible with SSTL_18 interface
• Fully differential clock inputs (CK, /CK) operation
• Double data rate interface
• Source synchronous-data transaction aligned to bidirectional data strobe (DQS, DQS)
• Differential Data Strobe (DQS, DQS)
• Data outputs on DQS, DQS edges when read (edged DQ)
• Data inputs on DQS centers when write(centered DQ)
• On chip DLL align DQ, DQS and DQS transition with CK transition
• DM mask write data-in at the both rising and falling edges of the data strobe
• All addresses and control inputs except data, data strobes and data masks latched on the rising edges of the clock
• Programmable CAS latency 3, 4, 5 and 6 supported
• Programmable additive latency 0, 1, 2, 3, 4 and 5 supported
• Programmable burst length 4 / 8 with both nibble sequential and interleave mode
• Internal four bank operations with single pulsed RAS
• Auto refresh and self refresh supported
• tRAS lockout supported
• 8K refresh cycles /64ms
• JEDEC standard 60ball FBGA(x4/x8) & 84ball FBGA(x16)
• Full strength driver option controlled by EMRS
• On Die Termination supported
• Off Chip Driver Impedance Adjustment supported
• Read Data Strobe supported (x8 only)
• Self-Refresh High Temperature Entry
• Partial Array Self Refresh support
Operating Frequency
Ordering Information
Speed Bin tCK(ns) CL tRCD tRP Unit
Part No.
Organization
Package
E3
C4
Y4
Y5
S5
S6
Clk
Clk
Clk
Clk
Clk
Clk
5
3.75
3
3
4
4
5
5
6
3
4
4
5
5
6
3
4
4
5
5
6
HY5PS12421B(L)FP-X*
128Mx4
64Mx8
HY5PS12821B(L)FP-X*
Lead free**
HY5PS121621B(L)FP-X*
32Mx16
3
Note:
1. -X* is the speed bin, refer to the Operation Frequency table for
complete Part No.
2. Hynix Lead-free products are compliant to RoHS.
2.5
2.5
Rev. 0.7 / Oct. 2007
4
HYNIX [ HYNIX SEMICONDUCTOR ]
