1HY5PS12421B(L)FP
1HY5PS12821B(L)FP
1HY5PS121621B(L)FP
3.2 DC & AC Logic Input Levels
3.2.1 Input DC Logic Level
Symbol
Parameter
Min.
Max.
Units
Notes
Notes
VIH(dc)
VREF + 0.125
VDDQ + 0.3
V
dc input logic high
dc input logic low
VIL(dc)
- 0.3
VREF - 0.125
V
3.2.2 Input AC Logic Level
DDR2 400,533
DDR2 667,800
Symbol
Parameter
Units
Min.
Max.
Min.
Max.
VREF +
0.250
VREF +
0.200
VIH (ac)
VIL (ac)
-
-
V
V
ac input logic high
ac input logic low
-
VREF - 0.250
-
VREF - 0.200
3.2.3 AC Input Test Conditions
Symbol
Condition
Value
Units
Notes
VREF
VSWING(MAX)
SLEW
Input reference voltage
Input signal maximum peak to peak swing
Input signal minimum slew rate
0.5 * VDDQ
1.0
V
V
1
1
1.0
V/ns
2, 3
Note:
1. Input waveform timing is referenced to the input signal crossing through the VREF level applied to the device
under test.
2. The input signal minimum slew rate is to be maintained over the range from VREF to VIH(ac) min for rising
edges and the range from VREF to VIL(ac) max for falling edges as shown in the below figure.
3. AC timings are referenced with input waveforms switching from VIL(ac) to VIH(ac) on the positive transitions
and VIH(ac) to VIL(ac) on the negative transitions.
VDDQ
VIH(ac) min
VIH(dc) min
VREF
VSWING(MAX)
V
IL(dc) max
VIL(ac) max
VSS
delta TF
delta TR
VREF - VIL(ac) max
delta TF
VIH(ac) min - VREF
Falling Slew =
Rising Slew =
delta TR
< Figure : AC Input Test Signal Waveform>
Rev. 0.7 / Oct. 2007
12
HYNIX [ HYNIX SEMICONDUCTOR ]
