HY57V161610ET-I
FUNCTIONAL BLOCK DIAGRAM
1Mx16 Synchronous DRAM
Self Refresh Counter
Row Addr. Latch/Predecoder
Auto/Self Refresh
Refresh
Interval Timer
Refresh
Counter
Row Decoder
Address[0:10]
Ref. Addr.[0:11]
512Kx16
Bank 0
Sense AMP & I/O gates
Column Decoder
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
CLK
Row Active
BA(A11)
CS
RAS
CAS
WE
UDQM
LDQM
Column Active
Overflow
Column Addr.
Latch & Counter
Burst Length
Counter
Column Decoder
Sense AMP & I/O gates
Row Addr. Latch/Predecoder
512Kx16
Bank 1
Mode Register
Test Mode
I/O Control
Rev. 0.1 / Nov. 2003
Data Input/Output Buffers
CKE
Precharge
Address
Register
State Machine
3
HYNIX [ HYNIX SEMICONDUCTOR ]
