GMS90 Series
TIMER / COUNTER 0 AND 1
Timer/Counter 0 and 1 can be used in four operating modes as listed in Table 4:
Table 4. Timer/Counter 0 and 1 Operating Modes
TMOD
Input Clock
Mode
Description
Gate
C/T
M1
M0
internal
external (Max.)
8-bit timer/counter with a
divide-by-32 prescaler
f
OSC ÷(12×32)
fOSC ÷(24×32)
0
1
2
X
X
0
0
f
f
OSC ÷12
OSC ÷12
f
f
OSC ÷24
OSC ÷24
16-bit timer/counter
X
X
0
1
8-bit timer/counter with
8-bit auto-reload
X
X
1
0
Timer/counter 0 used as
one 8-bit timer/counter and
one 8-bit timer Timer 1
stops
f
OSC ÷12
f
OSC ÷24
3
X
X
1
1
In the "timer" function (C/T = "0") the register is incremented every machine cycle. Therefore the count rate is
OSC/12.
f
In the "counter" function the register is incremented in response to a 1-to-0 transition at its corresponding exter-
nal input pin (P3.4/T0, P3.5/T1). Since it takes two machine cycles to detect a falling edge the max. count rate
is fOSC/24. External inputs INT0 and INT1 (P3.2, P3.3) can be programmed to function as a gate to facilitate
pulse width measurements. Figure 2 illustrates the input clock logic.
f
÷
12
OSC
f
÷ 12
OSC
C/T
TMOD
0
Timer 0/1
Input Clock
P3.4/T0
P3.5/T1
1
Max. f
/24
OSC
TR0 / 1
TCON
&
Gate
=1
TMOD
≥1
P3.2 / INT0
P3.3 / INT1
Figure 2. Timer/Counter 0 and 1 Input Clock Logic
Dec. 1998 Ver 3.0
19
HYNIX [ HYNIX SEMICONDUCTOR ]
