GMS90 Series
HYUNDAI MicroElectronics
1) Capacitive loading on ports 0 and 2 may cause spurious noise pulses to be superimposed on the V of ALE and port 3.
OL
The noise is due to external bus capacitance discharging into the port 0 and port 2 pins when these pins make 1-to-0 tran-
sitions during bus operation. In the worst case (capacitive loading: > 50pF at 3.3V, > 100pF at 5V), the noise pulse on ALE
line may exceed 0.8V. In such cases it may be desirable to qualify ALE with a schmitt-trigger, or use an address latch with
a schmitt-trigger strobe input.
2) Capacitive loading on ports 0 and 2 may cause the V on ALE and PSEN to momentarily fall below the 0.9V specifica-
OH
CC
tion when the address lines are stabilizing.
3) I Max at other frequencies is given by:
CC
active mode: I = 1.27 × f
+ 5.73
CC
OSC
idle mode:
where f
I
= 0.28 × f
+ 1.45 (except OTP devices)
CC
OSC
is the oscillator frequency in MHz. I values are given in mA and measured at V = 5V.
OSC
CC
CC
4) I (active mode) is measured with:
CC
XTAL1 driven with t
, t
= 5ns, V = V + 0.5V, V = V - 0.5V; XTAL2 = N.C.;
CLCH CHCL IL SS IH CC
EA = Port0 = RESET = V ; all other pins are disconnected. I would be slightly higher if a crystal oscillator is used (appr.
CC
CC
1mA).
5) I (Idle mode) is measured with all output pins disconnected and with all peripherals disabled;
CC
XTAL1 driven with t
, t
= 5ns, V = V + 0.5V, V = V - 0.5V; XTAL2 = N.C.;
CLCH CHCL IL SS IH CC
RESET = EA = V ; Port0 = V ; all other pins are disconnected;
SS
CC
6) I (Power Down Mode) is measured under following conditions:
PD
EA = Port0 = V ; RESET = V ; XTAL2 = N.C.; XTAL1 = V ; all other pins are disconnected.
CC
SS
SS
Oct. 2000 Ver 3.1a
27
HYNIX [ HYNIX SEMICONDUCTOR ]
