GMS81C2020/GMS81C2120
Hyundai Micro Electronics
14. Basic Interval Timer
The GMS81C2020 and GMS81C2120 has one 8-bit Basic
Interval Timer that is free-run, can not stop. Block diagram
is shown in Figure 14-1 .The 8-bit Basic interval timer reg-
ister (BITR) is increased every internal count pulse which
is divided by prescaler. Since prescaler has divided ratio by
8 to 1024, the count rate is 1/8 to 1/1024 of the oscillator
frequency. As the count overflows from FFH to 00H, this
overflow causes to generate the Basic interval timer inter-
rupt. The BITIF is interrupt request flag of Basic interval
timer.
cillator, prescaler ( only fXI÷2048 ) and Timer0.
If the STOP instruction executed after writing "1" to bit
RCWDT of CKCTLR, it goes into the internal RC oscillat-
ed watchdog timer mode. In this mode, all of the block is
halted except the internal RC oscillator, Basic Interval
Timer and Watchdog Timer. More detail informations are
explained in Power Saving Function. The bit WDTON de-
cides Watchdog Timer or the normal 7-bit timer
Note: All control bits of Basic interval timer are in CKCTLR
register which is located at same address of BITR
(address ECH). Address ECH is read as BITR, writ-
ten to CKCTLR. Therefore, the CKCTLR can not be
accessed by bit manipulation instruction.
When write "1" to bit BTCL of CKCTLR, BITR register is
cleared to "0" and restart to count-up. The bit BTCL be-
comes "0" after one machine cycle by hardware.
If the STOP instruction executed after writing "1" to bit
WAKEUP of CKCTLR, it goes into the wake-up timer
mode. In this mode, all of the block is halted except the os-
.
WAKEUP
STOP
RCWDT
BTS[2:0]
MUX
8
÷
÷
÷
÷
÷
÷
÷
BTCL
Clear
To Watchdog Timer
16
32
64
0
1
fXI
128
256
512
Basic Interval Timer
Interrupt
BITIF
BITR ( 8-BIT )
1024
÷
Internal RC OSC
Figure 14-1 Block Diagram of Basic Interval Timer
Clock Control Register
ADDRESS : ECH
RESET VALUE : -0010111
Bit Manipulation Not Available
-
WAKEUP RCWDT WDTON
Function Description
BTCL
BTS2
BTS1
BTS0
CKCTLR
Basic Interval Timer Clock Selection
000 : fXI
Symbol
8
÷
001 : fXI 16
÷
1: Enables Wake-up Timer
0: Disables Wake-up Timer
WAKEUP
010 : fXI 32
÷
011 : fXI 64
÷
1: Enables Internal RC Watchdog Timer
0: Disables Internal RC Watchdog Timer
RCWDT
WDTON
BTCL
100 : fXI 128
÷
101 : fXI 256
÷
1: Enables Watchdog Timer
0: Operates as a 7-bit Timer
110 : fXI 512
÷
111 : fXI 1024
÷
1: BITR is cleared and BTCL becomes "0" automatically
after one machine cycle, and BITR continue to count-up
Figure 14-2 CKCTLR : Clock Control Register
50
preliminary
Nov. 1999 Ver 0.0
HYNIX [ HYNIX SEMICONDUCTOR ]
