GMS81C5108
10. CLOCK GENERATOR
As shown in Figure 10-1, the clock generator produces the
basic clock pulses which provide the system clock to be
supplied to the CPU and the peripheral hardware. It con-
tains two oscillators: a main-frequency clock oscillator and
a sub-frequency clock oscillator. Power consumption can
be reduced by switching them to the low power operation
frequency clock can be easily obtained by attaching a res-
onator between the XIN and XOUT pin and the SXIN and
SXOUT pin, respectively. The system clock can also be ob-
tained from the external oscillator.
Instruction cycle time
CPU clock
fMAIN = 4MHz
fSUB = 32.768kHz
61 us
÷ 2
÷ 8
0.5 us
2.0 us
244 us
÷ 16
÷ 64
4.0 us
488 us
16.0 us
1953 us
To the peripheral block, the clock among the not-divided
original clocks, divided by 2, 4,..., up to 1024 can be pro-
vided. Peripheral clock is enabled or disabled by STOP in-
struction. The peripheral clock is controlled by clock
control register (CKCTLR). See "11. BASIC INTERVAL
TIMER" on page 43 for details.
The clock generator produces the system clocks forming
clock pulse, which are supplied to the CPU and the periph-
eral hardware. The internal system clock can be selected
by bit2, and bit3 of the system clock mode register (SC-
MR). The registers are shown in Figure 10-2.
SYCC<1>
SYCC<0>
** Clock is frozen by STOP or SLEEP[SMR.0] Instruction.
** Clock is released
1) by BIT overflow when previos state has been STOP mode.
2) by interrupts when previos state has been SLEEP mode.
SLEEP Mode
STOP Mode
SCS[1:0]
select clock
OSC Stop
÷2
÷8
X
IN
0
1
Internal system clock
MUX
÷16
÷64
SX
IN
PRESCALER
PS0
PS1
PS2
PS3
PS4
PS5
PS6
PS7
PS8
PS9
PS10
÷1
÷2
÷4
÷8
÷16
÷32
÷64 ÷128 ÷256 ÷512 ÷1024
Peripheral clock
f
(Hz)
PS0
4M
PS1
2M
PS2
PS3
PS4
250K
4u
PS5
125K
8u
PS6
62.5K
16u
PS7
PS8
PS9
7.183K 3.906K
128u 256u
PS10
EX
Frequency
period
1M
1u
500K
2u
31.25K 15.63K
4M
250n
500n
32u
64u
Figure 10-1 Block Diagram of Clock Generator
34
JUNE 2001 Ver 1.0
HYNIX [ HYNIX SEMICONDUCTOR ]
