GMS81C5108
9. I/O PORTS
The GMS81C5108 has seven ports (R0, R1, R2 and R3),
and LCD segment port (SEG0~SEG36), and LCD com-
mon port (COM0~COM3).
These ports pins may be multiplexed with an alternate
function for the peripheral features on the device.
9.1 Registers for Port
Port Data Registers
pull-up port. It is connected or disconnected by Pull-up
Control register (RnPU). The value of that resistor is typi-
cally 100kΩ. Refer to DC characteristics for more details.
The Port Data Registers (R0, R1, R2, R3) are represented
as a D-Type flip-flop, which will clock in a value from the
internal bus in response to a “write to data register” signal
from the CPU. The Q output of the flip-flop is placed on
the internal bus in response to a “read data register” signal
from the CPU. The level of the port pin itself is placed on
the internal bus in response to “read data register” signal
from the CPU. Some instructions that read a port activating
the “read register” signal, and others activating the “read
pin” signal.
When a port is used as key input, input logic is firmly ei-
ther low or high, therefore external pull-down or pull-up
resisters are required practically. The GMS81C5108 has
internal pull-up, it can be logic high by pull-up that can be
able to configure either connect or disconnect individually
by pull-up control registers RnPU.
When ports are configured as inputs and pull-up resistor is
selected by software, they are pulled to high.
Port Direction Registers
All pins have data direction registers which can define
these ports as output or input. A “1” in the port direction
register configure the corresponding port pin as output.
Conversely, write “0” to the corresponding bit to specify it
as input pin. For example, to use the even numbered bit of
R0 as output ports and the odd numbered bits as input
ports, write “55H” to address 0C8H (R0 port direction reg-
ister) during initial setting as shown in Figure 9-1.
VDD
VDD
PULL-UP RESISTOR
PORT PIN
Pull-up control bit
0: Disconnect
1: Connect
GND
All the port direction registers in the GMS81C5108 have 0
written to them by reset function. On the other hand, its in-
itial status is input.
Figure 9-2 Pull-up Port Structure
Open drain port Registers
WRITE “55 ” TO PORT R0 DIRECTION REGISTER
H
The R0, R1, R2 and R3 ports have open drain port resistors
R0CR~R3CR.
Figure 9-3 shows an open drain port configuration by control reg-
ister. It is selected as either push-pull port or open-drain port by
R0CR, R1CR, R2CR and R3CR.
0C0
0C1
H
H
BIT
R0 DATA
R1 DATA
0
7
1
6
0
5
1
4
0
3
1
2
0
1
1
0
~
~
~
~
0C8
0C9
R0 DIRECTION
R1 DIRECTION
H
H
I
O
6
I
O
4
I
O
2
I
O
0
PORT
7
5
3
1
I : INPUT PORT
O : OUTPUT PORT
PORT PIN
Open drain port selection bit
0: Push-pull
1: Open drain
Figure 9-1 Example of port I/O assignment
Pull-up Control Registers
GND
The R0, R1,R2 and R3 ports have internal pull-up resis-
tors. Figure 9-2 shows a functional diagram of a typical
Figure 9-3 Open-drain Port Structure
JUNE 2001 Ver 1.0
31
HYNIX [ HYNIX SEMICONDUCTOR ]
