GMS81C2012/GMS81C2020
19. RESET
HYUNDAI MicroElectronics
The GMS81C20xx have two types of reset generation pro-
cedures; one is an external reset input, the other is a watch-
dog timer reset. Table 19-1 shows on-chip hardware ini-
tialization by reset action.
On-chip Hardware
Initial Value
On-chip Hardware
Peripheral clock
Initial Value
(FFFFH) - (FFFEH)
Program counter
(PC)
(RPR)
(G)
Off
Disable
RAM page register
G-flag
0
Watchdog timer
Control registers
Power fail detector
0
Refer to Table 8-1 on page 32
Disable
Operation mode
Main-frequency clock
Table 19-1 Initializing Internal Status by Reset Action
19.1 External Reset Input
The reset input is the RESET pin, which is the input to a
Schmitt Trigger. A reset in accomplished by holding the
RESET pin low for at least 8 oscillator periods, within the
operating voltage range and oscillation stable, it is applied,
and the internal state is initialized. After reset, 64ms (at 4
MHz) add with 7 oscillator periods are required to start ex-
ecution as shown in Figure 19-2.
A connection for simple power-on-reset is shown in Figure
19-1.
VCC
10k
Ω
to the RESET pin
7036P
Internal RAM is not affected by reset. When VDD is turned
on, the RAM content is indeterminate. Therefore, this
RAM should be initialized before read or tested it.
+
10uF
When the RESET pin input goes to high, the reset opera-
tion is released and the program execution starts at the vec-
tor address stored at addresses FFFEH - FFFFH.
Figure 19-1 Simple Power-on-Reset Circuit
1
2
3
4
5
6
7
Oscillator
(X pin)
IN
RESET
ADDRESS
BUS
FFFE FFFF Start
?
?
?
?
?
DATA
BUS
OP
ADH
FE
ADL
?
?
?
MAIN PROGRAM
RESET Process Step
1
Stabilization Time
ST = 62.5mS at 4.19MHz
t
tST
=
x 256
fMAIN 1024
÷
Figure 19-2 Timing Diagram after RESET
19.2 Watchdog Timer Reset
Refer to “11. WATCHDOG TIMER” on page 45.
86
MAR. 2000 Ver 1.00
HYNIX [ HYNIX SEMICONDUCTOR ]
