GMS81C2012/GMS81C2020
HYUNDAI MicroElectronics
Interrupt (overflow) Period (ms)
CKCTLR
[2:0]
Source clock
XIN÷8
@ fXIN = 4MHz
f
f
f
f
f
f
f
f
000
001
010
011
100
101
110
111
0.512
1.024
2.048
4.096
8.192
16.384
32.768
65.536
XIN÷16
XIN÷32
XIN÷64
XIN÷128
XIN÷256
XIN÷512
XIN÷1024
Table 10-1 Basic Interval Timer Interrupt Time
7
-
6
5
4
3
2
1
0
ADDRESS: 0ECH
INITIAL VALUE: -001 0111B
WDTONBTCL
WAKEUP RCWDT
BTCL BTS2 BTS1 BTS0
CKCTLR
Basic Interval Timer source clock select
000: fXIN ÷ 8
001: fXIN ÷ 16
010: fXIN ÷ 32
011: fXIN ÷ 64
100: fXIN ÷ 128
101: fXIN ÷ 256
110: fXIN ÷ 512
111: fXIN ÷ 1024
Clear bit
0: Normal operation (free-run)
Caution:
Both register are in same address,
when write, to be a CKCTLR,
when read, to be a BITR.
1: Clear 8-bit counter (BITR) to “0”. This bit becomes 0 automatically
after one machine cycle, and starts counting.
0: Operate as a 7-bit general timer
1: Enable Watchdog Timer operation
See the section “Watchdog Timer”.
0: Disable Internal RC Watchdog Timer
1: Enable Internal RC Watchdog Timer
0: Disable Wake-up Timer
1: Enable Wake-up Timer
7
6
5
4
3
2
1
0
ADDRESS: 0ECH
INITIAL VALUE: Undefined
BTCL
BITR
8-BIT FREE-RUN BINARY COUNTER
Figure 10-2 BITR: Basic Interval Timer Mode Register
Example 1:
Example 2:
Basic Interval Timer Interrupt request flag is generated
every 4.096ms at 4MHz.
Basic Interval Timer Interrupt request flag is generated
every 1.024ms at 4MHz.
:
:
LDM
CKCTLR,#03H
LDM
CKCTLR,#01H
SET1 BITE
EI
:
SET1 BITE
EI
:
44
MAR. 2000 Ver 1.00
HYNIX [ HYNIX SEMICONDUCTOR ]
