HYUNDAI MicroElectronics
GMS82512/16/24
10. BASIC INTERVAL TIMER
The GMS825xx has one 8-bit Basic Interval Timer that is
free-run and can not stop. Block diagram is shown in Fig-
ure 10-1.
generated. The Basic Interval Timer is controlled by the
clock control register (CKCTLR) shown in Figure 10-2.
Source clock can be selected by lower 3 bits of CKCTLR.
In addition, the Basic Interval Timer generates the time
base for watchdog timer counting. It also provides a Basic
interval timer interrupt (BITIF). As the count overflow
from FFH to 00H, this overflow causes the interrupt to be
BITR and CKCTLR are located at same address, and ad-
dress 0D3H is read as a BITR, and written to CKCTLR.
÷16
÷32
8-bit up-counter
BITR
÷64
source
clock
÷128
÷256
÷512
÷1024
÷2048
overflow
X
PIN
IN
BITIF
MUX
Basic Interval Timer Interrupt
[0F9 ]
H
To Watchdog timer (WDTCK)
clear
3
Select Input clock
BTS[2:0]
CKCTLR
BTCL
[0D3 ]
H
Read
Basic Interval Timer
clock control register
Internal bus line
Figure 10-1 Block Diagram of Basic Interval Timer
Interrupt (overflow) Period (ms)
CKCTLR
[2:0]
Source clock
XIN÷16
@ fXIN = 8MHz
f
f
f
f
f
f
f
f
000
001
010
011
100
101
110
111
0.512
1.024
2.048
4.096
8.192
16.384
32.768
65.536
XIN÷32
XIN÷64
XIN÷128
XIN÷256
XIN÷512
XIN÷1024
XIN÷ 2048
Table 10-1 Basic Interval Timer Interrupt Time
FEB. 2000 Ver 1.00
31
HYNIX [ HYNIX SEMICONDUCTOR ]
