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GMS82524 参数 Datasheet PDF下载

GMS82524图片预览
型号: GMS82524
PDF下载: 下载PDF文件 查看货源
内容描述: 8位单芯片微控制器 [8-BIT SINGLE-CHIP MICROCONTROLLERS]
分类和应用: 微控制器
文件页数/大小: 93 页 / 1003 K
品牌: HYNIX [ HYNIX SEMICONDUCTOR ]
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GMS82512/16/24  
HYUNDAI MicroElectronics  
[Zero flag Z]  
or data transfer is “0” and is cleared by any other result.  
This flag is set when the result of an arithmetic operation  
MSB  
LSB  
N
V
G
B
H
I
Z
C
RESET VALUE: 00  
PSW  
NEGATIVE FLAG  
H
CARRY FLAG RECEIVES  
CARRY OUT  
OVERFLOW FLAG  
ZERO FLAG  
SELECT DIRECT PAGE  
when G=1, page is selected to “page 1”  
INTERRUPT ENABLE FLAG  
HALF CARRY FLAG RECEIVES  
CARRY OUT FROM BIT 1 OF  
BRK FLAG  
ADDITION OPERLANDS  
Figure 8-3 PSW (Program Status Word) Register  
This flag assigns RAM page for direct addressing mode. In  
[Interrupt disable flag I]  
the direct addressing mode, addressing area is from zero  
page 00H to 0FFH when this flag is "0". If it is set to "1",  
addressing area is assigned 100H to 1FFH. It is set by  
SETG instruction and cleared by CLRG.  
This flag enables/disables all interrupts except interrupt  
caused by Reset or software BRK instruction. All inter-  
rupts are disabled when cleared to “0”. This flag immedi-  
ately becomes “0” when an interrupt is served. It is set by  
the EI instruction and cleared by the DI instruction.  
[Overflow flag V]  
[Half carry flag H]  
This flag is set to “1” when an overflow occurs as the result  
of an arithmetic operation involving signs. An overflow  
occurs when the result of an addition or subtraction ex-  
ceeds +127(7FH) or -128(80H). The CLRV instruction  
clears the overflow flag. There is no set instruction. When  
the BIT instruction is executed, bit 6 of memory is copied  
to this flag.  
After operation, this is set when there is a carry from bit 3  
of ALU or there is no borrow from bit 4 of ALU. This bit  
can not be set or cleared except CLRV instruction with  
Overflow flag (V).  
[Break flag B]  
This flag is set by software BRK instruction to distinguish  
BRK from TCALL instruction with the same vector ad-  
dress.  
[Negative flag N]  
This flag is set to match the sign bit (bit 7) status of the re-  
sult of a data or arithmetic operation. When the BIT in-  
struction is executed, bit 7 of memory is copied to this flag.  
[Direct page flag G]  
16  
FEB. 2000 Ver 1.00  
 
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