GMS81C2012/GMS81C2020
HYUNDAI MicroElectronics
MSB
N
LSB
C
V
G
B
H
I
Z
RESET VALUE : 00H
PSW
NEGATIVE FLAG
CARRY FLAG RECEIVES
CARRY OUT
OVERFLOW FLAG
ZERO FLAG
SELECT DIRECT PAGE
when G=1, page is selected to “page 1”
INTERRUPT ENABLE FLAG
HALF CARRY FLAG RECEIVES
CARRY OUT FROM BIT 1 OF
BRK FLAG
ADDITION OPERLANDS
Figure 8-3 PSW (Program Status Word) Register
This flag assigns RAM page for direct addressing mode. In
[Interrupt disable flag I]
the direct addressing mode, addressing area is from zero
page 00H to 0FFH when this flag is "0". If it is set to "1",
addressing area is assigned 100H to 1FFH. It is set by
SETG instruction and cleared by CLRG.
This flag enables/disables all interrupts except interrupt
caused by Reset or software BRK instruction. All inter-
rupts are disabled when cleared to “0”. This flag immedi-
ately becomes “0” when an interrupt is served. It is set by
the EI instruction and cleared by the DI instruction.
[Overflow flag V]
[Half carry flag H]
This flag is set to “1” when an overflow occurs as the result
of an arithmetic operation involving signs. An overflow
occurs when the result of an addition or subtraction ex-
ceeds +127(7FH) or -128(80H). The CLRV instruction
clears the overflow flag. There is no set instruction. When
the BIT instruction is executed, bit 6 of memory is copied
to this flag.
After operation, this is set when there is a carry from bit 3
of ALU or there is no borrow from bit 4 of ALU. This bit
can not be set or cleared except CLRV instruction with
Overflow flag (V).
[Break flag B]
This flag is set by software BRK instruction to distinguish
BRK from TCALL instruction with the same vector ad-
dress.
[Negative flag N]
This flag is set to match the sign bit (bit 7) status of the re-
sult of a data or arithmetic operation. When the BIT in-
struction is executed, bit 7 of memory is copied to this flag.
[Direct page flag G]
26
MAR. 2000 Ver 1.00
HYNIX [ HYNIX SEMICONDUCTOR ]
