Chapter 4. FUNCTIONAL DESCRIPTION
Watch Dog Timer (WDT)
Watch dog timer is organized binary of 14 steps. The signal of fOSC/6 cycle comes
in the first step of WDT after WDT reset. If this counter was overflowed, reset
signal automatically come out so that internal circuit is initialized.
The overflow time is 6 2 13/fOSC (108.026ms at fOSC=455KHz.)
8 6 213/fOSC (108.026ms at fOSC = 3.64MHz)
Normally, the binary counter must be reset before the overflow by using reset
instruction (WDTR), Power-on reset pulse or Low VDD detection pulse.
* It is constantly reset in STOP mode. When STOP is released, counting is
restarted.
Binary counter(14 steps)
fOSC/6 or fOSC/48
RESET (edge-trigger)
CPU reset
Reset
by instruction
Power-On Reset
Low VDD Detection
Fig. 4-7 Block Diagram of Watch-dog Timer
4-10
HYNIX [ HYNIX SEMICONDUCTOR ]
