Chapter 4. FUNCTIONAL DESCRIPTION
Reset Operation
GMS36/37XXX has three reset sources. One is a built-in Power-on reset circuit, another
is a built-in Low VDD Detection circuit, the other is the overflow of Watch Dog Timer. (WDT)
All reset operations are internal in the GMS36/37XXX.
Built-in Power On Reset Circuit
GMS36/37XXX has a built-in Power-on reset circuit consisting of an about 1 Resistor
and a 3pF Capacitor. When the Power-on reset pulse occurs, system reset signal is
latched and WDT is cleared. After the overflow time of WDT (213 x System clock time)
system reset signal is released.
<GMS36/37XXX>
VCC
System
RESETB
treset
About 108msec at
fosc = 455kHz
Fig. 4-4 Power-On Reset Circuit and Timing Chart
4-8
HYNIX [ HYNIX SEMICONDUCTOR ]
