Chapter 3. Instruction
(39) RO
Naming :
Status :
Reset Output Register Latch
Set
¥°
D(Y)
Format :
Function :
¡ ç
¡ Â ¡ Â
Y 7
0
0
¡ ç
0
REMOUT
0
Y = 8
Y = 9
¡ ç
D0~D9
¡ ç
0
¡ Â ¡ Â
Y Dh
Y = Eh
Y = Fh
R(Y)
¡ ç
0
Ah
R
¡ ç
D0~D9, R
0
<Purpose>
A single D output line is set to logic 0, if data of Y-register is
between 0 to 9.
REMOUT port is set to logic 0, if data of Y-register is 9.
All D output line is set to logic 0, if data of Y-register is 9.
When Y is between Ah and Dh, one of R output lines is set at
logic 0.
When Y is Eh, the output of R is set at logic 0
When Y is Fh, the output D0~D9 and R are set at logic 1.
Data of Y-register is between 0 to 7, selects appropriate D
output.
<Comment>
Data of Y-register is 8, selects REMOUT port.
Data of Y-register is 9, selects D port.
Data in Y-register, when between Ah and Dh, selects an
appropriate R output (R0~R3).
Data in Y-register, when it is Eh, selects all of R0~R3.
Data in Y-register, when it is Fh, selects all of D0~D9 and
R0~R3.
(40) WDTR
Naming :
Status :
Watch Dog Timer Reset
Set
¥°
Format :
Function :
<Purpose>
Reset Watch Dog Timer (WDT)
Normally, you should reset this counter before overflowed
counter for dc watch dog timer. this instruction controls this
reset signal.
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HYNIX [ HYNIX SEMICONDUCTOR ]
