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GMS30012-XXXDT 参数 Datasheet PDF下载

GMS30012-XXXDT图片预览
型号: GMS30012-XXXDT
PDF下载: 下载PDF文件 查看货源
内容描述: [Microcontroller, 4-Bit, MROM, 1MHz, CMOS, PDSO20, SOP-20]
分类和应用: 时钟微控制器光电二极管外围集成电路
文件页数/大小: 158 页 / 972 K
品牌: HYNIX [ HYNIX SEMICONDUCTOR ]
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Chapter 2. Architecture  
Initial Reset Circuit  
RESET pin must be down to L more than 4 machine cycle by outside  
capacitor or other for power on reset.  
The mean of 1 machine cycle is below. 1 machine cycle is 6/fOSC, however,  
operating voltage must be in recommended operating conditions, and clock  
oscillating stability.  
* It is required to adjust C value depending on rising time of power supply.  
(Example shows the case of rising time shorter than 10ms.)  
1
RESET  
0.1uF  
Watch Dog Timer (WDT)  
Watch dog timer is organized binary counter of 14 steps. The selected of  
fOSC/6 cycle come in the first step of WDT. If this counter was overflowed, come  
out reset signal automatically, internal circuit is initialized.  
The overflow time is 6 213/fOSC (108.026ms at fOSC = 455KHz).  
Normally, the binary counter must be reset before the overflow by using reset  
instruction (WDTR) or / and REMOUT port (Y-reg=8, SO instruction execution) at  
masked option.  
* It is constantly reset in STOP mode. When STOP is released, counting is  
restarted. (Refer to 1-13 STOP function>)  
Binary counter  
(14 steps)  
RESET (edge-trigger)  
CPU reset  
fOSC/6  
Reset  
by instruction  
REMOUT  
output  
Mask Option  
2 - 7  
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