GM76C256C Series
Notes(WRITE CYCLE):
1. A write occurs during the overlap of a low /CS and a low /WE. A write begins at the latest transition
among /CS going low and /WE going low: A write ends at the earliest transition among /CS going high
and /WE going high. t
WP
is measured from the beginning of write to the end of write.
2. t
CW
is measured from the later of /CS going low to the end of write .
3. t
AS
is measured from the address valid to the beginning of write.
4. t
WR
is measured from the end of write to the address change. t
WR is
applied in case a write ends as /CS,
or /WE going high.
5. If /OE and /WE are in the read mode during this period, and the I/O pins are in the output low-Z state,
input of opposite phase of the output must not be applied because bus contention can occur.
6. If /CS goes low simultaneously with /WE going low, or after /WE going low, the outputs remain in high
impedance state.
7. D
OUT
is the same phase of the latest written data in this write cycle.
8. D
OUT
is the read data of the new address.
DATA RETENTION CHARACTERISTIC
T
A
= 0°C to 70°C (Normal) / -25°C to 85°C (Extended) unless otherwise specified.
Symbol
Parameter
Test Condition
Min
V
DR
Vcc for Data Retention
CS>Vcc-0.2V,
2.0
V
IN
> Vcc - 0.2V or V
IN
< Vss + 0.2V
I
CCDR
Data Retention Current
Vcc=3.0V,
L
-
/CS>Vcc - 0.2V,
LL
-
V
IN
> Vcc - 0.2V or
LE
-
V
IN
< Vss + 0.2V
LLE
-
tCDR
Chip Deselect to Data
See Data Retention
0
Retention Time
tR
Operating Recovery Time
Timing Diagram
tRC
(2)
Notes
1. Typical values are under the condition of T
A
= 25
°C.
2. tRC is read cycle time.
Typ
-
1
0.5
1
0.5
-
-
Max
-
15
7
20
10
-
-
Unit
V
uA
uA
uA
uA
ns
ns
DATA RETENTION TIMING DIAGRAM
VCC
4.5V
tCDR
DATA RETENTION MODE
tR
2.2V
VDR
CS>VCC-0.2V
CS
VSS
Rev 03 / Apr. 2000
7
HYNIX [ HYNIX SEMICONDUCTOR ]
