GM76C256CL/LL
Write Cycle 2
(/CS Controlled) (Note 1, 2, 3)
t
WC
ADD
t
AS
t
CW
/CS
t
AW
t
WP
/WE
t
WR
t
DW
D
IN
VALID DATA
t
DH
D
OUT
High-Z
Notes:
1. The internal write time of the memory is defined by the overlap of /CS low and /WE low. Both signals
must be low to initiate a write and either signal can terminate a write by going high. The data input
set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.
2. Data I/O is high impedance if /OE = V
IH
.
3. If /CS goes high simultaneously with /WE high, the output remains in a high impedance state.
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