GM72V66841ET/ELT
Block Diagram
A0 to A13
A0 to A8
A0 to A13
Column address
counter
Column address
buffer
Row address
counter
Refresh
counter
Row decoder
Row decoder
Row decoder
Row decoder
Column decoder
Sense amplifier & I/O bus
Column decoder
Sense amplifier & I/O bus
Column decoder
Sense amplifier & I/O bus
Memory array
Bank 0
4096 row
x 512 column
x 8 bit
Memory array
Bank 1
4096 row
x 512 column
x 8 bit
Memory array
Bank 2
4096 row
x 512 column
x 8 bit
Column decoder
Sense amplifier & I/O bus
Memory array
Bank 3
4096 row
x 512 column
x 8 bit
Input
buffer
Output
buffer
Control logic &
timing generator
RAS
CAS
WE
CKE
CLK
DQ0 to DQ7
DQM
-2-
Rev. 1.1/Apr.01
CS