GM71V17403C
GM71VS17403CL
14.
t
WCS
,
t
RWD
,
t
CWD
,
t
AWD
and
t
CPW
are not restrictive operating parameters. They are included in the
data sheet as electrical characteristics only; if
t
WCS
>=
t
WCS
(min), the cycles is an early write cycle
and the data out pin will remain open circuit (high impedance) throughout the entire cycle; if
t
RWD
>=
t
RWD
(min), the
t
CWD
>=
t
CWD
(min), and
t
AWD
>=
t
AWD
(min), or
t
CWD
>=
t
CWD
(min),
t
AWD
>=
t
AWD
(min) and
t
CPW
>=
t
CPW
(min), the cycle is a read-modify-write and the data output will contain
data read from the selected cell; if neither of the above sets of conditions is satisfied, the
condition of the data out (at access time) is indeterminate.
15. These parameters are referenced to CAS leading edge in early write cycles and to WE leading
edge in delayed write or read-modify-write cycles.
16.
t
RASP
defines RAS pulse width in EDO page mode cycles.
17. Access time is determined by the longest among
t
AA
or
t
CAC
or
t
ACP
.
18. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the
4M x 4 are don't care during test mode. Test mode is set by performing a WE-and-CAS-before-
RAS (WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O
(I/O1 to I/O4) and read out from each I/O. If 4 bits of each I/O are equal (all 1s or 0s), data
output pin is a high state during test mode read cycle, then the device has passed. If they are not
equal, data output pin is a low state, then the device has failed. Refresh during test mode
operation can be performed by normal read cycles or by WCBR refresh cycles. To get out of test
mode and enter a normal operation mode, perform either a regular CAS-before-RAS refresh
cycle or RAS-only refresh cycle.
19. In a test mode read cycle, the value of
t
RAC
,
t
AA
,
t
CAC
and
t
ACP
is delayed by 2ns to 5ns for the
specified value. These parameters should be specified in test mode cycles by adding the above
value to the specified value in this data sheet.
20. t
HPC
(min) can be achieved during a series of EDO page mode write cycles or EDO page mode
read cycles. If both write and read operation are mixed in a EDO page mode RAS cycle(EDO
page mode mix cycle (1),(2)), minimum value of CAS cycle (t
CAS
+ t
CP
+ 2t
T
) becomes greater
than the specified t
HPC
(min) value. The value of CAS cycle time of mixed EDO page mode is
shown in EDO page mode mix cycle (1) and (2).
Rev 0.1 / Apr’01
HYNIX [ HYNIX SEMICONDUCTOR ]
