GM71C18163C
GM71CS18163CL
Recommended DC Operating Conditions
(T
A
= 0 ~
+
70C)
Symbol
V
CC
V
IH
V
IL
Parameter
Supply Voltage
Input High Voltage
Input Low Voltage
Min
4.5
2.4
-1.0
Typ
5.0
-
-
Max
5.5
6.0
0.8
Unit
V
V
V
Note: All voltage referred to Vss.
The supply voltage with all VCC pins must be on the same level. The supply voltage with all VSS pins must be
on the same level.
Truth Table
RAS
H
L
L
L
L
L
L
L
L
L
L
L
L
H to L
H to L
H to L
L
L
LCAS
D
L
H
L
L
H
L
L
H
L
L
H
L
H
L
L
H
L
UCAS
D
H
L
L
H
L
L
H
L
L
H
L
L
L
H
L
H
L
WE
D
H
H
H
L
L
L
L
L
L
H to L
H to L
H to L
D
D
D
D
H
OE
D
L
L
L
D
D
D
H
H
H
L to H
L to H
L to H
D
D
D
D
H
Output
Open
Valid
Valid
Valid
Open
Open
Open
Undefined
Undefined
Undefined
Valid
Valid
Valid
Open
Open
Open
Open
Open
Operation
Standby
Lower byte
Upper byte
Word
Lower byte
Upper byte
Word
Lower byte
Upper byte
Word
Lower byte
Upper byte
Word
Word
Word
Word
Word
CBR Refresh
or
Self Refresh
(L-series)
RAS-only
Refresh cycle
Read-modify
-write cycle
Delayed Write
cycle
Early write cycle
Read cycle
Notes
1,3
1,3
1,2,3
1,2,3
1,3
1,3
1,3
1,3
Read cycle
(Output disabled)
Notes: 1. H: High (inactive) L: Low(active) D: H or L
2.
t
WCS
>= 0ns Early write cycle
t
WCS
<= 0ns Delayed write cycle
3. Mode is determined by the OR function of the UCAS and LCAS. (Mode is set by earliest of
UCAS and LCAS active edge and reset by the latest of UCAS and LCAS inactive edge.) However
write OPERATION and output High-Z control are done independently by each UCAS,LCAS.
ex) if RAS = H to L, UCAS = H, LCAS = L, then CAS-before-RAS refresh cycle is selected.
Rev 0.1 / Apr’01
HYNIX [ HYNIX SEMICONDUCTOR ]
