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TJ4519 参数 Datasheet PDF下载

TJ4519图片预览
型号: TJ4519
PDF下载: 下载PDF文件 查看货源
内容描述: 600kHz的3A降压型开关稳压器 [600kHz 3A Step-Down Switching Regulator]
分类和应用: 稳压器开关
文件页数/大小: 11 页 / 478 K
品牌: HTC [ HTC KOREA TAEJIN TECHNOLOGY CO. ]
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600kHz 3A Step-Down Switching Regulator  
ID-AVG = IOMAX (I-D)  
TJ4519  
Thermal Considerations  
There are three major power dissipation sources for the TJ4519. The internal switch conduction loss its  
switching loss due to the high frequency switching actions and the base drive boost circuit loss. These losses can  
be estimated as:  
10  
P
= IO2 Ron D+10.810-3 IO • V +  
IO D•(Vboost )  
total  
I
1000  
Where:  
IO = load current;  
Ron = on-equivalent resistance of the switch;  
VBOOST = input voltage or output based on the boost circuit connection.  
The junction temperature of the TJ4519 can be further determined by:  
TJ = TA + θJA P  
total  
θ
JA is the thermal resistance from junction to ambient. Its value is a function of the IC package, the application  
layout and the air cooling system.  
The freewheeling diode also contributes a significant portion of the total converter loss. This loss should be  
minimized to increase the converter efficiency by using Schottky diodes with low forward drop (VF).  
Pdiode = VF IO (1-D)  
Loop Compensation Design  
The TJ4519 has an internal error amplfier and requires a compensation network to connect between the  
COMP pin and GND pin as shown in Figure 3. The compensation network includes C4, C5 and R3. R1 and R2  
are used to program the output voltage according to:  
R1  
VO = 0.8(1+  
)
R2  
Assuming the power stage ESR (equivalent series resistance) zero is an order of magnitude higher than the  
closed loop bandwidth, which is typically one tenth of the switching frequency, the power stage control to output  
transfer function with the current loop closed (Ridley model) for the TJ4519 will be as follows:  
2.5 RL  
GVD(s) =  
s
1+  
1
RL • C  
Where:  
RL = Load,  
C = Output capacitor.  
The goal of the compensation design is to shape the loop to have a high DC gain, high bandwidth, enough phase  
margin, and high attenuation for high frequency noises. Figure 3 gives a typical compensation network which  
offers 2 poles and 1 zero to the power stage:  
Jul. 2010 – Preliminary  
- 9 -  
HTC  
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