DDR VDDQ and VTT Termination Voltage Regulator
TJ3212
The VDDQ power supply, in addition to supplying current to the memory banks, could also supply current to
controllers and other circuitry. The current level typically stays within a range of 0.5A to 1A, with peaks up to 2A or
more, depending on memory size and the computing operations being performed.
The tight tracking requirements and the need for VTT to sink, as well as source, current provide unique challenges
for powering DDR SDRAM.
TJ3212 Regulator
The TJ3212 dual output linear regulator provides all of the power requirements of DDR memory by combining two
linear regulators into a single package. VDDQ regulator can supply up to 2A current, and the two quadrant VTT
termination regulator has current sink and source capability to ± 2A. The VDDQ linear regulator uses a PMOS pass
element for a very low dropout voltage, typically 500mV at a 2A output. The output voltage of VDDQ can be set by
an external voltage divider. The use of regulators for both the upper and lower side of the VDDQ output allows a
fast transient response to any change of the load, from high current to low current or inversely. The second output,
VTT, is regulated at VDDQ / 2 by an internal resistor divider. Same as VDDQ, VTT has the same fast transient
response to load change in both directions. The VTT regulator can source, as well as sink, up to 2A current. The
TJ3212 is designed for optimal operation from a nominal 3.3V DC bus, but can work with VIN up to 5V. When
operating at higher VIN voltages, attention must be given to the increased package power dissipation and
proportionally increased heat generation. Limited by the package thermal resistance, the maximum output current
of the device at higher VIN cannot exceed the limit imposed by the maximum power dissipation value.
VREF is typically routed to inputs with high impedance, such as a comparator, with little current draw. An adequate
VREF can be created with a simple voltage divider of precision, matched resistors from VDDQ to ground. A small
ceramic bypass capacitor can also be added for improved noise performance.
Input and Output Capacitors
The TJ3212 requires that at least a 220uF electrolytic capacitor be located near the VIN pin for stability and to
maintain the input bus voltage during load transients. An additional 4.7uF ceramic capacitor between the VIN and
GND, located as close as possible to those pins, is recommended to ensure stability.
At a minimum, a 220uF electrolytic capacitor is recommended for the VDDQ output. An additional 4.7uF ceramic
capacitor between the VDDQ and GND, located very close to those pins, is recommended.
At a minimum, a 220uF electrolytic capacitor is recommended for the VTT output. This capacitor should have low
ESR to achieve best output transient response. SP or OSCON capacitors provide low ESR at high frequency, and
thus are a good choice. In addition, place a 4.7uF ceramic capacitor between the VTT pin and GND, located very
close to those pins. The total ESR must be low enough to keep the transient within the VTT window of 40mV
during the transition for source to sink. An average current step of ± 0.5A requires:
40mV
ESR <
= 40mΩ
1A
Both outputs will remain stable and in regulation even during light or no load conditions. The general
recommendation for circuit stability for the TJ3212 requires the following:
1) CIN = CDDQ = CTT = 220uF / 4.7uF for the full temperature range of –40 to +85°C.
2) CIN = CDDQ = CTT = 100uF / 2.2uF for the temperature range of –25 to +85°C.
Mar. 2011 - Preliminary
- 10 -
HTC
HTC [ HTC KOREA TAEJIN TECHNOLOGY CO. ]
