DDR Termination Regulator
DESCRIPTION
TJ2995
The TJ2995 is a linear bus termination regulator designed to meet the JEDEC requirements of SSTL-2
and SSTL-3. The TJ2995 is capable of sinking and sourcing current at the output V
TT
, regulating the
voltage to equal V
DDQ
/ 2. A buffered reference voltage that also tracks V
DDQ
/ 2 is generated on the V
REF
pin for providing a global reference to the DDR-SDRAM and Northbridge Chipset. V
TT
is designed to
track the V
REF
voltage with a tight tolerance over the entire current range while preventing shoot through
on the output stage.
Series Stub Termination Logic (SSTL) was created to improve signal integrity of the data transmission
across the memory bus. This termination scheme is essential to prevent data error from signal reflections
while transmitting at high frequencies encountered with DDR RAM. The most common form of termination
is Class II single parallel termination. This involves using one RS series resistor from the chipset to the
memory and one RT termination resistor. This implementation can be seen below in Figure 1.
FIGURE 1. SSTL-Termination Scheme
PIN DESCRIPTION
AV
IN
AND PV
IN
AV
IN
and PV
IN
are the input supply pins for the TJ2995. AV
IN
is used to supply all the internal control
circuitry for the two op-amps and the output stage of V
REF
. PV
IN
is used exclusively to provide the rail
voltage for the output stage on the power operational amplifier used to create V
TT
. For SSTL-2
applications AV
IN
and PV
IN
pins should be connected directly and tied to the 2.5V rail for optimal
performance. This eliminates the need for bypassing the two supply pins separately.
V
DDQ
V
DDQ
is the input used to create the internal reference voltage for regulating V
TT
. The reference
voltage is generated from a resistor divider of two internal 50㏀ resistors. This guarantees that V
TT
will
track V
DDQ
/ 2 precisely. The optimal implementation of V
DDQ
is as a remote sense. This can be
achieved by connecting V
DDQ
directly to the 2.5V rail at the DIMM instead of AV
IN
and PV
IN
. This ensures
that the reference voltage tracks the DDR memory rails precisely without a large voltage drop from
the power lines. For SSTL-2 applications V
DDQ
will be a 2.5V signal, which will create a 1.25V
termination voltage at V
TT
(See Electrical Characteristics Table for exact values of V
TT
over
temperature).
Oct. 2009 - Rev. 1.1
5/9
HTC
HTC [ HTC KOREA TAEJIN TECHNOLOGY CO. ]
