DDR Termination Regulator
PCB LAYOUT CONSIDERATIONS
TJ2995
1. AV
IN
and PV
IN
should be tied together for optimal performance. A local bypass capacitor should be
placed as close as possible to the PV
IN
pin.
2. GND should be connected to a ground plane with multiple vias for improved thermal performance.
3. V
SENSE
should be connected to the V
TT
termination bus at the point where regulation is required. For
motherboard applications an ideal location would be at the center of the termination bus.
4. V
DDQ
can be connected remotely to the V
DDQ
rail input at either the DIMM or the Chipset. This provides
the most accurate point for creating the reference voltage.
5. V
REF
should be bypassed with a 0.01
μF
or 0.1
μF
ceramic capacitor for improved performance. This
capacitor should be located as close as possible to the V
REF
pin.
Oct. 2009 - Rev. 1.1
9/9
HTC
HTC [ HTC KOREA TAEJIN TECHNOLOGY CO. ]
