DDR Termination Regulator
TJ2997
VTT is distributed across a long plane it is advisable to use multiple bulk capacitors and addition to high
frequency decoupling. Figure 9 shown below depicts an example circuit where 2 bulk output capacitors
could be situated at both ends of the VTT plane for optimal placement. Large aluminum electrolytic
capacitors are used for their low ESR and low cost.
FIGURE 11. Typical SSTL-2 Application Circuit for Motherboards
In most PC applications an extensive amount of decoupling is required because of the long
interconnects encountered with the DDR-SDRAM DIMMs mounted on modules. As a result bulk
aluminum electrolytic capacitors in the range of 1000uF are typically used.
PCB LAYOUT CONSIDERATIONS
1. The input capacitor for the power rail should be placed as close as possible to the PVIN pin.
2. VSENSE should be connected to the VTT termination bus at the point where regulation is required. For
mother- board applications an ideal location would be at the center of the termination bus.
3. VDDQ can be connected remotely to the VDDQ rail input at either the DIMM or the Chipset. This provides
the most accurate point for creating the reference voltage.
4. For improved thermal performance excessive top side copper should be used to dissipate heat from
the package. Numerous vias from the ground connection to the internal ground plane will help.
Additionally these can be located underneath the package if manufacturing standards permit.
5. Care should be taken when routing the VSENSE trace to avoid noise pickup from switching I/O signals. A
0.1uF ceramic capacitor located close to the SENSE can also be used to filter any unwanted high
frequency signal. This can be an issue especially if long SENSE traces are used.
6. VREF should be bypassed with a 0.01µF or 0.1µF ceramic capacitor for improved performance. This
capacitor should be located as close as possible to the VREF pin.
Apr, 2011 - R1.0.1
13/13
HTC
HTC [ HTC KOREA TAEJIN TECHNOLOGY CO. ]
