1.5A, 280kHz, Boost Regulator
LM5171
The high frequency pole, fP2, can be placed at the output filter’s ESR zero or at half the switching frequency.
Placing the pole at this frequency will cut down on switching noise. The frequency of this pole is determined by
the value of C2 and R1:
1
f p2
=
2πC2R1
One simple method to ensure adequate phase margin is to design the frequency response with a −20dB per
decade slope, until unity−gain crossover. The crossover frequency should be selected at the midpoint between
fZ1 and fP2 where the phase margin is maximized.
Frequency (Log)
Figure 24. Bode Plot of the Compensation Network shown in Figure 23.
VSW Voltage Limit
In the boost topology, VSW pin maximum voltage is set by the maximum output voltage plus the output diode
forward voltage. The diode forward voltage is typically 0.5V for Schottky diodes and 0.8V for ultra fast
recovery diodes
VSW(MAX) = VOUT(MAX) + VF
where:
VF = output diode forward voltage.
In the flyback topology, peak VSW voltage is governed by:
VSW(MAX) = VCC(MAX) + (VOUT + VF) ⅹ N
where:
N = transformer turns ratio, primary over secondary.
When the power switch turns off, there exists a voltage spike superimposed on top of the steady−state
voltage. Usually this voltage spike is caused by transformer leakage inductance charging stray capacitance
between the VSW and PGND pins. To prevent the voltage at the VSW pin from exceeding the maximum rating,
a transient voltage suppressor in series with a diode is paralleled with the primary windings. Another method
of clamping switch voltage is to connect a transient voltage suppressor between the VSW pin and ground.
Dec. 2010 - Rev. 1.2.1
- 12 -
HTC
HTC [ HTC KOREA TAEJIN TECHNOLOGY CO. ]
