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HDSP-2107 参数 Datasheet PDF下载

HDSP-2107图片预览
型号: HDSP-2107
PDF下载: 下载PDF文件 查看货源
内容描述: 八字符5毫米和7毫米智能字母数字显示器 [Eight Character 5 mm and 7 mm Smart Alphanumeric Displays]
分类和应用: 显示器光电
文件页数/大小: 16 页 / 408 K
品牌: HP [ HEWLETT-PACKARD ]
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12  
UDC RAM and UDC Address  
Register  
Figure 3 shows the logic levels  
needed to access the UDC RAM  
and the UDC Address Register.  
The UDC Address Register is  
eight bits wide. The lower four  
bits (D0-D3) are used to select one  
of the 16 UDC locations. The  
upper four bits (D4-D7) are not  
used. Once the UDC address has  
been stored in the UDC Address  
Register, the UDC RAM can be  
accessed.  
To completely specify a 5 x 7  
character, eight write cycles are  
required. One cycle is used to  
store the UDC RAM address in the  
UDC Address Register and seven  
cycles are used to store dot data  
in the UDC RAM. Data is entered  
by rows and one cycle is needed  
to access each row. Figure 4  
shows the organization of a UDC  
character assuming the symbol to  
be stored is an “F.” A0-A2 are used  
to select the row to be accessed  
and D0-D4 are used to transmit  
the row dot data. The upper three  
bits (D5-D7) are ignored. D0 (least  
significant bit) corresponds to the  
right most column of the 5 x 7  
matrix and D4 (most significant  
bit) corresponds to the left most  
column of the 5 x 7 matrix.  
Figure 3. Logic Levels to Access a UDC Character.  
C
O
L
1
C
O
L
2
C
O
L
3
C
O
L
4
C
O
L
5
Flash RAM  
UDC  
CHARACTER  
HEX  
D4 D3 D2 D1 D0  
CODE  
Figure 5 shows the logic levels  
needed to access the Flash RAM.  
The Flash RAM has one bit  
associated with each location of  
the Character RAM. The Flash  
input is used to select the Flash  
RAM while address lines A3-A4 are  
ignored. Address lines A0-A2 are  
used to select the location in the  
Flash RAM to store the attribute.  
D0 is used to store or remove the  
flash attribute. D0 = “1” stores  
the attribute and D0 = “0”  
1
1
1
1
1
1
1
1
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
1
0
0
0
1
0
0
0
0
0
0
ROW 1  
ROW 2  
ROW 3  
ROW 4  
ROW 5  
ROW 6  
ROW 7  
*
*
*
*
*
*
*
*
*
*
*
1F  
10  
10  
1D  
10  
10  
10  
*
*
*
IGNORED  
0 = LOGIC 0; 1 = LOGIC 1; * = ILLUMINATED LED.  
Figure 4. Data to Load ""F'' into the UDC RAM.  
When the attribute is enabled  
through bit 3 of the Control Word  
and a “1” is stored in the Flash  
RAM, the corresponding  
mately 2 Hz. The actual rate is  
dependent on the clock frequency.  
For an external clock the flash  
rate can be calculated by dividing  
the clock frequency by 28,672.  
removes the attribute.  
character will flash at approxi-