3
Table 1a. Truth Table for CDR at Entry Configurations
FM_LOOP = FM_NODE[0], TO_LOOP = TO_NODE[0], BYPASS[0]– = 1
TO_LOOP
FM_LOOP
FM_NODE[1]
TO_NODE[1]
FM_LOOP
FM_LOOP
BYPASS[1]–
0
1
Table 1b. Truth Table for CDR at Exit Configurations
FM_LOOP = FM_NODE[1], TO_LOOP = TO_NODE[1], BYPASS[1]– = 1
TO_LOOP
FM_LOOP
FM_NODE[0]
TO_NODE[0]
FM_LOOP
FM_LOOP
BYPASS[0]–
0
1
Table 2. Pin Connection Diagram to Achieve Desired
CDR Location (see Figures 4 and 5)
X Denotes CDR Position with respect to Hard Disks
Hard Disk
Connection to PBC Cells
CDR Position (x)
Cell Connected to Cable
A
1
xA
0
A
0
Ax
1
FM_NODE[1]–
FM_NODE[1]+
V
CC
HS
TO_NODE[1]–
TO_NODE[1]+
GND
GND
BYPASS[1]–
SD[1]
V
CC
GND
CPLL1
1
2
3
4
5
6
7
8
9
10
11
12
24
23
22
21
FM_NODE[0]–
FM_NODE[0]+
V
CC
HS
TO_NODE[0]–
TO_NODE[0]+
GND
GND
BYPASS[0]–
SD[0]
V
CC
A
REFCLK
CPLL0
HDMP-0421
R x.YY
nnnn-nnn
S YYWW
COUNTRY
20
19
18
17
16
15
14
13
nnnn.nnn = WAFER LOT - BUILD NUMBER (1-3 DIGITS)
Rx.yy = DIE REVISION
S = SUPPLIER CODE
YYWW = DATE CODE (YY = YEAR, WW = WORK WEEK)
COUNTRY = COUNTRY OF MANUFACTURE
Figure 3: HDMP-0421 Package Layout and Marking, Top View.
HP [ AGILENT(HEWLETT-PACKARD) ]
