10
strobing the blank input). All of
these blanking modes affect only
the output drivers, maintaining
the contents and write capability
of the internal RAMs and Control
Register, so that normal loading
of RAMs and Control Register can
take place even with the display
blanked.
EFD
0
MB
0
DBD
BL
0
n
–Display Blanked by BL
–Display ON
0
0
0
0
X
1
1
0
X
–Display Blanked by BL.
Individual Characters “ON”
based on “1” being stored in DBD
n
n
Figure 3 shows how the Extended
Function Disable (bit D6 of the
Control Register), Master Blank
(bit D2 of the Control Register),
Digit Blank Disable (bit D1 of the
Attribute RAM), and BL input can
be used to blank the display.
0
0
1
1
0
1
X
1
–Display Blanked by MB
–Display Blanked by MB.
Individual characters “ON”
based on “1” being stored in DBD
–Display Blanked by BL
–Display ON
1
1
X
X
X
X
0
1
When the Extended Function
Disable is a logic 1, the display
can be blanked only with the
BL input. When the Extended
Function Disable is a logic 0, the
display can be blanked through
the BL input, the Master Blank,
and the Digit Blank Disable. The
entire display will be blanked if
either the BL input is logic 0 or
the Master Blank is logic 1, pro-
viding all Digit Blank Disable
bits are logic 0. Those digits with
Digit Blank Disable bits a logic 1
will ignore both blank signals
and remain ON. The Digit Blank
Disable bits allow individual
characters to be blanked or
flashed in synchronization with
the BL input.
Figure 3. Display Blanking Truth Table.
Bits 3–5 in the Control Register
provide internal brightness
Dimming
Dimming of the display is con-
trolled through either the BL
input or the Control Register. A
pulse width modulated signal can
be applied to the BL input to dim
the display. A three bit word in
the Control Register generates an
internal pulse width modulated
signal to dim the display. The
internal dimming feature is
control. These bits are interpreted
as a three bit binary code, with
code (000) corresponding to the
maximum brightness and code
(111) to the minimum brightness.
In addition to varying the display
brightness, bits 3–5 also vary the
average value of IDD. IDD can be
specified at any brightness level
as shown in Table 1.
enabled only if the Extended
Function Disable is a logic 0.
Table 1. Current Requirements at Different Brightness Levels
Symbol D5 D4 D3
Brightness
25°C Typ.
25°C Max.
Max. over Temp. Units
IDD(#)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
100%
60%
40%
27%
17%
10%
7%
110
66
45
30
20
12
9
130
79
53
37
24
15
11
6
160
98
66
46
31
20
15
9
mA
mA
mA
mA
mA
mA
mA
mA
3%
4
HP [ HEWLETT-PACKARD ]
