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HCPL-5431 参数 Datasheet PDF下载

HCPL-5431图片预览
型号: HCPL-5431
PDF下载: 下载PDF文件 查看货源
内容描述: 密封式,超高速逻辑门光电耦合器 [Hermetically Sealed, Very High Speed, Logic Gate Optocouplers]
分类和应用: 光电输出元件
文件页数/大小: 12 页 / 246 K
品牌: HP [ HEWLETT-PACKARD ]
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MIL-PRF-38534 Class H,  
Class K, and DESC SMD  
Test Program  
Hewlett-Packard’s Hi-Rel Opto-  
couplers are in compliance with  
MIL-PRF-38534 Classes H and K.  
Class H devices are also in  
Data Rate and Pulse-  
Width Distortion  
Definitions  
Propagation delay is a figure of  
merit which describes the finite  
amount of time required for a  
system to translate information  
from input to output when  
When tPLH and tPHL differ in  
value, pulse width distortion  
results. Pulse width distortion is  
defined as |tPHL - tPLH| and  
determines the maximum data  
rate capability of a distortion-  
limited system. Maximum pulse  
width distortion on the order of  
25-35% is typically used when  
specifying the maximum data rate  
capabilities of systems. The exact  
figure depends on the particular  
application (RS-232, PCM, T-1,  
etc.).  
compliance with DESC drawings  
5962-89570, and 5962-89571.  
shifting logic levels. Propagation  
delay from low to high (tPLH  
)
Testing consists of 100% screen-  
ing and quality conformance  
inspection to MIL-PRF-38534.  
specifies the amount of time  
required for a system’s output to  
change from a Logic 0 to a Logic  
1, when given a stimulus at the  
input. Propagation delay from  
high to low (tPHL) specifies the  
amount of time required for a  
system’s output to change from a  
Logic 1 to a Logic 0, when given  
a stimulus at the input (see  
Figure 5).  
These high performance opto-  
couplers offer the advantages of  
specified propagation delay (tPLH  
tPHL), and pulse width distortion  
(|tPLH -t PHL|) over temperature  
,
and power supply voltage ranges.  
Applications  
V
= +5 V  
CC1  
30 pF  
HCPL-5400  
226 Ω  
274 Ω  
V
= 5 V  
CC2  
V
CC  
0.1 µF  
DATA  
IN  
DATA  
OUT  
TTL  
A
LSTTL  
STTL  
Y
HCMOS  
GND 1  
GND  
TOTEM  
POLE  
GND 2  
Y = A  
1
OUTPUT GATE  
(e.g. 54AS1000)  
2
Figure 13. Recommended HCPL-5400 Interface Circuit.  
1-534