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HCPL-540K 参数 Datasheet PDF下载

HCPL-540K图片预览
型号: HCPL-540K
PDF下载: 下载PDF文件 查看货源
内容描述: 密封式,超高速逻辑门光电耦合器 [Hermetically Sealed, Very High Speed, Logic Gate Optocouplers]
分类和应用: 光电输出元件
文件页数/大小: 12 页 / 246 K
品牌: HP [ AGILENT(HEWLETT-PACKARD) ]
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Notes:
1. Not to exceed 5% duty factor, not to exceed 50
µsec
pulse width.
2. All devices are considered two-terminal devices: measured between all input leads or terminals shorted together and all output leads
or terminals shorted together.
3. This is a momentary withstand test, not an operating condition.
4. t
PHL
propagation delay is measured from the 50% point on the rising edge of the input current pulse to the 1.5 V point on the falling
edge of the output pulse. The t
PLH
propagation delay is measured from the 50% point on the falling edge of the input current pulse to
the 1.5 V point on the rising edge of the output pulse. Pulse Width Distortion, PWD = |t
PHL
- t
PLH
|.
5. CM
L
is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the logic low state
(V
O(MAX)
< 0.8 V). CM
H
is the maximum slew rate of the common mode voltage that can be sustained with the output voltage in the
logic high state (V
O(MIN)
> 2.0 V).
6. Duration of output short circuit time not to exceed 10 ms.
7. Power Supply Noise Immunity is the peak to peak amplitude of the ac ripple voltage on the V
CC
line that the device will withstand and
still remain in the desired logic state. For desired logic high state, V
OH(MIN)
> 2.0 V, and for desired logic low state, V
OL(MAX)
< 0.8 V.
8. Measured between adjacent input pairs shorted together for each multichannel device.
9. Each channel.
10. Standard parts receive 100% testing at 25°C (Subgroups 1 and 9). SMD and hi-rel parts receive 100% testing at 25, 125, and –55°C
(Subgroups 1 and 9, 2 and 10, 3 and 11, respectively).
11. Parameters are tested as part of device initial characterization and after design and process changes. Parameters are guaranteed to
limits specified for all lots not specifically tested.
12. Propagation delay skew is defined as the difference between the minimum and maximum propagation delays for any given group of
optocouplers with the same part number that are all switching at the same time under the same operating conditions.
13. The HCPL-6430 and HCPL-6431 dual channel parts function as two independent single channel units. Use the single channel
parameter limits.
Figure 1. Typical Logic Low Output
Voltage vs. Logic Low Output Current.
Figure 2. Typical Logic High Output
Voltage vs. Logic High Output Current.
Figure 3. Typical Output Voltage vs.
Input Forward Current.
Figure 4. Typical Diode Input Forward
Current Characteristic.
1-531