4
Package Pin Out
1
2
3
4
5
6
7
8
V
V
V
V
16
15
IN+
E
V
IN-
LED2+
DESAT 14
CC1
GND1
V
13
12
11
10
9
CC2
RESET
FAULT
V
C
V
OUT
V
V
V
LED1+
EE
EE
V
LED1-
Pin Descriptions
Symbol
Description
Non-inverting gate drive voltage output
(V ) control input.
Symbol
Description
Common (IGBT emitter) output supply
voltage.
VIN+
VIN-
VE
OUT
Inverting gate drive voltage output
(V ) control input.
VLED2+ LED 2 anode. This pin must be left uncon-
nected for guaranteed data sheet
performance. (For optical coupling testing
only)
OUT
VCC1
Positive input supply voltage. (4.5 V to 5.5 V)
DESAT Desaturation voltage input. When the voltage
on DESAT exceeds an internal reference
voltage of 7 V while the IGBT is on, FAULT
output is changed from a high impedance
state to a logic low state within 5 µs. See
Note 25.
GND1 Input Ground.
VCC2
VC
Positive output supply voltage.
RESET FAULT reset input. A logic low input for at
least 0.1 µs, asynchronously resets FAULT
output high and enables VIN. Synchronous
control of RESET relative to VIN is required.
RESET is not affected by UVLO. Asserting
RESET while VOUT is high does not affect
Collector of output pull-up triple-darlington
transistor. It is connected to VCC2 directly or
through a resistor to limit output turn-on
current.
VOUT
.
FAULT Fault output. FAULT changes from a high
impedance state to a logic low output within
5 µs of the voltage on the DESAT pin
exceeding an internal reference voltage of
7 V. FAULT output remains low until RESET
is brought low. FAULT output is an open
collector which allows the FAULT outputs
from all HCPL-316Js in a circuit
V
OUT
Gate drive voltage output.
to be connected together in a “wired OR”
forming a single fault bus for interfacing
directly to the micro-controller.
VLED1+ LED 1 anode. This pin must be left uncon-
nected for guaranteed data sheet per-
VEE
Output supply voltage.
formance. (For optical coupling testing only)
VLED1- LED 1 cathode. This pin must be connected
to ground.
HP [ HEWLETT-PACKARD ]
