250
C = 15 pF INCLUDING PROBE
V
= 5 V
L
CC
PULSE
GENERATOR
AND JIG CAPACITANCES
.
C1 (120 pF) PEAKING
CAPACITOR IS USED.
SEE FIGURE 5.
I
(mA)
5
3
F
+5 V
V
Z
= 50 Ω
CC
O
200
150
t = t
= 5 ns
r
f
1.6
V
HCPL-2200
V
O
S1
1.6
3
5
1
2
3
4
8
7
6
5
CC
619 Ω
D
t
1
PHL
I
F
D
2
100
50
C
L
5 kΩ
D
3
t
PLH
GND
INPUT V
D
4
C
-60 -40 -20
0
20 40 60 80 100
MONITORING
NODE
T
– TEMPERATURE – °C
A
S2
D
ARE 1N916 OR 1N3064.
1-4
Figure 6. Typical Propagation Delays
vs. Temperature.
3.0 V
INPUT
1.3 V
0 V
V
E
t
t
PLZ
PZL
S1 AND
S2 CLOSED
0.5 V
0.5 V
OUTPUT
S1 CLOSED
S2 OPEN
1.3 V
V
O
V
V
OL
t
PZH
OH
≈1.5 V
OUTPUT
1.3 V
0 V
V
O
S1 OPEN
S2 CLOSED
S1 AND
S2 CLOSED
t
PHZ
Figure 7. Test Circuit for t
, t
, t
, and t
.
PZL
PHZ PZH PLZ
100
200
120
100
80
V
20 V
C
= 15 pF
CC
V
C
= 5 V
= 15 pF
L
CC
2
C
= 15 pF
L
V
CC
80
60
40
150
100
4.5 V
20 V
t
PHZ
t
PLZ
PZL
4.5 V
20 V
60
t
t
r
4.5 V
40
t
20 V
50
0
20
0
4.5 V
20
0
t
PZH
f
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40 60 80 100
-60 -40 -20
0
20 40 60 80 100
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
T
– TEMPERATURE – °C
A
A
A
Figure 8. Typical Logic Low Enable
Propagation Delay vs. Temperature.
Figure 10. Typical Rise, Fall Time vs.
Temperature.
Figure 9. Typical Logic High Enable
Propagation Delay vs. Temperature.
1-129
HP [ HEWLETT-PACKARD ]
